Manufacturing Test Engineer

About the Team:

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role

We are seeking a Manufacturing Test Engineer to own and drive manufacturing test strategy, development, and execution for complex AI hardware systems. This role will define and implement test coverage across the product lifecycle, including ICT, functional circuit test, tray-level functional test, and system manufacturing test.

You will work closely with hardware design engineering, diagnostic/software teams, manufacturing engineering, quality, and external system integrators and suppliers to translate product requirements into robust, scalable, and production-ready test solutions. You will also play a key role in reviewing test data, debugging failures, improving yield, and ensuring manufacturing test readiness from early development through volume production.

In This Role, You Will:

• Define and drive the manufacturing test strategy for boards, trays, and system-level hardware assemblies across EVT, DVT, PVT, and production ramp.

• Develop and manage test coverage for:

  • ICT / structural test

  • FCT / board-level functional test

  • Tray-level functional and integration test

  • System-level manufacturing and bring-up test

• Partner closely with electrical engineering, system engineering, and diagnostic/software teams to define test requirements, review manufacturing test scripts and diagnostics, validate failure isolation needs, debug hooks, logging, and production screening strategies.

• Translate engineering requirements into practical, scalable manufacturing test plans that balance coverage matrices; review and approve EVT/DVT/PVT and production test plans, pass/fail criteria and release gates while balancing coverage, test time, debug efficiency, cost, and production throughput.

• Collaborate with system integrators, JDMs, contract manufacturers, and equipment vendors to implement and qualify test stations, fixtures, automation, software, equipment configurations, calibration plans